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Preliminary Spec.
Specifications subject to change without notice.
MITSUBISHI LSIs
MH8V724AWZJ -5, -6
FAST PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM PIN CONFIGURATION
DESCRIPTION
The MH8V724AWZJ is 8388608-word x 72-bit dynamic ram module. This consist of nine industry standard 8M x 8 dynamic RAMs in SOJ and one industry standard EEPROM in TSSOP. The mounting of SOJs and TSSOP on a card edge dual in-line package provides any application where high densities and large of quantities memory are required. This is a socket-type memory module ,suitable for easy interchange or addition of module.
85pin 94pin 95pin
1pin 10pin 11pin
FEATURES
Type name
MH8V724AWZJ-5 MH8V724AWZJ-6
/RAS /CAS Address /OE access access access access time time time time Cycle time Power dissipation
(typ.W) (max.ns) (max.ns) (max.ns) (max.ns) (min.ns)
50 60
13 15
25 30
13 15
90 110
3.51 2.93
Utilizes industry standard 8M x 8 RAMs in SOJ and industry standard EEPROM in TSSOP 168-pin (84-pin dual dual in-line package) Single +3.3V(0.3V) supply operation Low stand-by power dissipation 9.72mW(Max) . . . . . . . . . . . . . . . . . . . LVCMOS input level Low operation power dissipation MH8V724AWZJ -5 . . . . . . . . . . . . . . . . . . 4.22W(Max) MH8V724AWZJ -6 . . . . . . . . . . . . . . . . . . 3.89W(Max) All input are directly LVTTL compatible All output are three-state and directly LVTTL compatible Includes(0.22uF x 9) decoupling capacitors 4096 refresh cycle every 64ms Fast-page mode,Read-modify-write, /CAS before /RAS refresh,Hidden refresh capabilities Gold plating contact pads
124pin BACK SIDE 125pin
40pin FRONT SIDE 41pin
Row Address A0 ~ A11 Column Address A0 ~ A10 168pin 84pin
APPLICATION
Main memory unit for computers , Microcomputer memory
MIT-DS-0094-0.5
MITSUBISHI ELECTRIC
( 1 / 20 )
27/Feb./1997
Preliminary Spec.
Specifications subject to change without notice.
MITSUBISHI LSIs
MH8V724AWZJ -5, -6
FAST PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM
Pin No.
PIN CONFIGURATION
Pin No.
Pin Name Vss DQ0 DQ1 DQ2 DQ3 Vcc DQ4 DQ5 DQ6 DQ7 DQ8 Vss DQ9 DQ10 DQ11 DQ12 DQ13 Vcc DQ14 DQ15 CB0 CB1 Vss NC NC Vcc /WE0 /CAS0 /CAS1 /RAS0 /OE0 Vss A0 A2 A4 A6 A8 A10 NC Vcc Vcc DU
Pin Name Vss /OE2 /RAS2 /CAS2 /CAS3 /WE2 Vcc NC NC CB2 CB3 Vss DQ16 DQ17 DQ18 DQ19 Vcc DQ20 NC DU NC Vss DQ21 DQ22 DQ23 Vss DQ24 DQ25 DQ26 DQ27 Vcc DQ28 DQ29 DQ30 DQ31 Vss NC NC NC SDA SCL Vcc
Pin No.
Pin Name Vss DQ32 DQ33 DQ34 DQ35 Vcc DQ36 DQ37 DQ38 DQ39 DQ40 Vss DQ41 DQ42 DQ43 DQ44 DQ45 Vcc DQ46 DQ47 CB4 CB5 Vss NC NC Vcc DU /CAS4 /CAS5 NC DU Vss A1 A3 A5 A7 A9 A11 NC Vcc DU DU
Pin No.
Pin Name Vss DU NC /CAS6 /CAS7 DU Vcc NC NC CB6 CB7 Vss DQ48 DQ49 DQ50 DQ51 Vcc DQ52 NC DU NC Vss DQ53 DQ54 DQ55 Vss DQ56 DQ57 DQ58 DQ59 Vcc DQ60 DQ61 DQ62 DQ63 Vss NC NC SA0 SA1 SA2 Vcc
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84
85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126
127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168
NC: No Connect DU: Don't Use
MIT-DS-0094-0.5
MITSUBISHI ELECTRIC
( 2 / 20 )
27/Feb./1997
Preliminary Spec.
Specifications subject to change without notice.
MITSUBISHI LSIs
MH8V724AWZJ -5, -6
FAST PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM
/RAS2 /WE2 /OE2
BLOCK DIAGRAM
/RAS0 /WE0 /OE0
/OE
/W
/RAS
/CAS0
M5M465800AJ
D0
/OE /W /RAS
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
/OE
/W
/RAS
/CAS4
M5M465800AJ
D5
/OE /W /RAS
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
/CAS1
M5M465800AJ
/CAS5
M5M465800AJ
D1
/OE /W /RAS
D6
/OE /W /RAS
M5M465800AJ
/CAS6
M5M465800AJ
D2
/OE /W /RAS
D7
/OE /W /RAS
/CAS2 M5M465800AJ
/CAS7 M5M465800AJ
D3
/OE /W /RAS
D8
/CAS3 M5M465800AJ
D4
A0~A11 Vcc Vss MIT-DS-0094-0.5 C0~C8 ...
D0~D8 SCL
D0~D8
EEPROM A0 A1 A2 SA0 SA1 SA2
SDA
MITSUBISHI ELECTRIC
( 3 / 20 )
27/Feb./1997
Preliminary Spec.
Specifications subject to change without notice.
MITSUBISHI LSIs
MH8V724AWZJ -5, -6
FAST PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM
Serial Presence Detect TABLE
Bytes 0 1 2 3 4 5 6 7 8 9 Function described Defines # bytes written into serial memory at module mfgr Total # bytes of SPD memory device Fundamental memory type # Row Addresses on this assembly # Column Addresses on this assembly # Module Banks on this assembly Data Width of this assembly... ... Data Width continuation Voltage interface standard of this assembly RAS# access time of this assembly -5 -6 10 CAS# access time of this assembly -5 -6 11 12 13 14 15-31 32-61 62 63 DIMM Configuration type (Non-parity,Parity,ECC) Refresh Rate/Type DRAM width,Primary DRAM Error Checking DRAM data width Reserved for future offerings Superset Memory type(may be used in future) SPD Data Revision Code Checksum for bytes 0-62 SPD entry data 128 256 Bytes FPM DRAM A0-A11 A0-A10 1bank x72 0 3.3V LVTTL 50ns 60ns 13ns 15ns ECC N/R(15.625uS) x8 x8 open open Rev 1 Check sum for -5 Check sum for -6 64-71 72 Manufacturers JEDEC ID code per JEP-106 Manufacturing location MITSUBISHI Miyoshi,Japan Tajima,Japan NC,USA Germany 73-90 Manufacturer's Part Number MH8V724AWZJ-5 MH8V724AWZJ-6 91-92 93-94 95-98 99-125 126-127 128-255 Revision Code Manufacturing date Assembly Serial Number Manufacturer Specific Data Reserved Open User Free-Form area not defined PCB revision year/week code serial number open open open SPD DATA entry(Hex) 80 08 01 0C 0B 01 48 00 02 32 3C 0D 0F 02 00 08 08 00 00 01 3D 49 1CFFFFFFFFFFFFFF 01 02 03 04 4D48385637323441575A4A2D352D352020202020 4D48385637323441575A4A2D362D362020202020 rrrr yy/ww ssssssss 00 00 00
MIT-DS-0094-0.5
MITSUBISHI ELECTRIC
( 4 / 20 )
27/Feb./1997
Preliminary Spec.
Specifications subject to change without notice.
MITSUBISHI LSIs
MH8V724AWZJ -5, -6
FAST PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM
a number of other functions, e.g., Fast page mode, /RASonly refresh, and delayed-write. The input conditions for each are shown in Table 1.
FUNCTION
The MH8V724AWZJ provide, in addition to normal read, write, and read-modify-write operations,
Table 1 Input conditions for each mode Operation Read Write (Early write) Write (Delayed write) Read-modify-write
/CAS before /RAS refresh
Inputs /RAS ACT ACT ACT ACT ACT NAC /CAS ACT ACT ACT ACT ACT DNC /W NAC ACT ACT ACT NAC DNC /OE ACT DNC DNC ACT DNC DNC Row Column address address APD APD APD APD APD APD APD APD DNC DNC DNC DNC
Input/Output Input OPN VLD VLD VLD DNC DNC Output VLD OPN IVD VLD OPN OPN
Refresh YES YES YES YES YES NO
Remark Fast page mode identical
Standby
Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : Invalid, APD : applied, OPN : open
MIT-DS-0094-0.5
MITSUBISHI ELECTRIC
( 5 / 20 )
27/Feb./1997
Preliminary Spec.
Specifications subject to change without notice.
MITSUBISHI LSIs
MH8V724AWZJ -5, -6
FAST PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM
Conditions With respect to Vss Ta=25C Ratings -0.5~ 4.6 50 9 0~70 -40~125 Unit V mA W C C
ABSOLUTE MAXIMUM RATINGS
Symbol Vcc IO Pd Topr Tstg Parameter Supply voltage Output current Power dissipation Operating temperature Storage temperature
RECOMMENDED OPERATING CONDITIONS
Symbol Vcc Vss VIH VIL Parameter Supply voltage Supply voltage High-level input voltage, all inputs Low-level input voltage Min 3.0 0 2.0 -0.3
(Ta=0~70C, unless otherwise noted) (Note 1)
Limits Nom Max 3.3 3.6 0 0
Vcc+0.3
Unit V V V V
0.8
Note 1 : All voltage values are with respect to Vss
ELECTRICAL CHARACTERISTICS
Symbol VOH VOL IOZ II Parameter
(Ta=0~70C, Vcc=3.3V0.3V, Vss=0V, unless otherwise noted) (Note 2)
Test conditions IOH=-2.0mA IOL=2.0mA Q floating 0V VOUT Vcc
0VVINVcc+0.3, Other input pins=0V 0VVINVcc+0.3, Other input pins=0V
High-level output voltage Low-level output voltage Off-state output current Input current (except /CAS) Input current (/CAS) I I (CAS) Average supply ICC1 (AV) current from Vcc operating ICC2
Min 2.4 0 -10 -90 -20
Limits Max Typ Vcc 0.4 10 90 20 1170 1080 9 4.5 900 810 1170 1080
Unit V V uA uA uA mA
-5 -6
(Note 3,4,5)
/RAS, /CAS cycling tRC=tWC=min. output open /RAS=/CAS =VIH, output open
/RAS=/CAS=WEVcc -0.2, output open
Supply current from Vcc , stand-by Average supply current from Vcc Fast-Page-Mode
mA mA
-5 -6 -5 -6
ICC4(AV)
(Note 3,4,5)
/RAS=VIL,/CAS cycling tPC=min. output open /CAS before /RAS refresh cycling tRC=min. output open
ICC6(AV)
Average supply current from Vcc /CAS before /RAS refresh (Note 3,5) mode
mA
Note 2: Current flowing into an IC is positive, out is negative. 3: Icc1 (AV), Icc3 (AV), Icc4 (AV) and Icc6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate. 4: Icc1 (AV) and Icc4 (AV) are dependent on output loading. Specified values are obtained with the output open. 5: Under condition of column address being changed once or less while /RAS=VIL and /CAS=VIH
CAPACITANCE
Symbol CI (/CAS) CI C(DQ) C(SCL) C(SDA) C(SA0~3)
(Ta = 0~70C, Vcc = 3.3V0.3V, Vss = 0V, unless otherwise noted)
Parameter Input capacitance, /CAS input Input capacitance, except /CAS input Input/Output capacitance,DATA Input capacitance, SPD clock Input/Output capacitance,SPD DATA Input capacitance, SPD address
Test conditions
Min
Limits Typ
VI=Vss f=1MHZ Vi=25mVrms
Max 20 80 15 7 7 7
Unit pF pF pF pF pF pF
MIT-DS-0094-0.5
MITSUBISHI ELECTRIC
( 6 / 20 )
27/Feb./1997
Preliminary Spec.
Specifications subject to change without notice.
MITSUBISHI LSIs
MH8V724AWZJ -5, -6
FAST PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM
(Ta=0~70C, Vcc=3.3V0.3V, Vss=0V, unless otherwise noted , see notes 6,13,14)
SWITCHING CHARACTERISTICS
Symbol tCAC tRAC tAA tCPA tOEA tCLZ tOFF tOEZ
Limits Parameter Min Access time from /CAS Access time from /RAS Column address access time Access time from /CAS precharge Access time from /OE Output low impedance time /CAS low Output disable time after /CAS high Output disable time after /OE high
(Note 7,8) (Note 7,9) (Note 7,10) (Note 7,11) (Note 7) (Note 7) (Note 12) (Note 12)
-5 Max 13 50 25 30 13 13 13 Min
-6 Max 15 60 30 35 15 15 15
Unit ns ns ns ns ns ns ns ns
5 0 0
5 0 0
Note 6: An initial pause of 500us is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles containing /CAS before /RAS refresh). Note the /RAS may be cycled during the initial pause . And any 8 /RAS or /RAS /CAS cycles are required after prolonged periods (greater than 64 ms) of /RAS inactivity before proper device operation is achieved. 7: Measured with a load circuit equivalent to 1 TTL load and 100pF.The reference levels for measuring of output signals are 2.0V(VOH)and 0.8V(VOL). 8: Assumes that tRCD tRCD(max), tASC tASC(max). 9: Assumes that tRCD tRCD(max) and tRAD tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC will increase by amount that tRCD exceeds the value shown. 10: Assumes that tRAD tRAD(max) and tASC tASC(max). 11: Assumes that tCP tCP(max) and tASC tASC(max). 12: tOFF (max) and tOEZ(max) defines the time at which the output achieves the high impedance state (IOUT I 10uA I ) and is not reference to VOH(min) or VOL(max).
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write ,Refresh, and Fast-Page Mode Cycles)
(Ta=0~70C, Vcc=3.3V0.3V, Vss=0V, unless otherwise noted ,see notes 13,14)
Limits Symbol tREF tRP tRCD tCRP tRPC tCPN tRAD tASR tASC tRAH tCAH tDZC tDZO tCDD tODD tT Parameter Min Refresh cycle time /RAS high pulse width Delay time, /RAS low to /CAS low (Note15) Delay time, /CAS high to /RAS low Delay time, /RAS high to /CAS low /CAS high pulse width Column address delay time from /RAS low (Note16) Row address setup time before /RAS low Column address setup time before /CAS low(Note17) Row address hold time after /RAS low Column address hold time after /CAS low Delay time, data to /CAS low (Note18) Delay time, data to /OE low (Note18) Delay time, /CAS high to data (Note19) Delay time, /OE high to data (Note19) Transition time (Note20) 30 14 5 0 8 10 0 0 8 8 0 0 13 13 1 -5 Max 64 37 40 14 5 0 10 12 0 0 10 10 0 0 15 15 1 Min -6 Max 64 45 ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
25 10
30 13
50
50
Note 13: The timing requirements are assumed tT =5ns. 14: VIH(min) and VIL(max) are reference levels for measuring timing of input signals.VIH(min) and VIL(max) of the switching characteristics are 2.0V and 0.8V respectively 15: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access time is controlled exclusively by tCAC or tAA.tRCD(min) is specified as tRCD(min) = tRAH(min) + 2tT + tASC(min) . 16: tRAD(max) is specified as a reference point only. If tRADtRAD(max) and tASCtASC(max), access time is controlled exclusively by tAA. 17: tASC(max) is specified as a reference point only. If tRCDtRCD(max) and tASCtASC(max), access time is controlled exclusively by tCAC. 18: Either tDZC or tDZO must be satisfied. 19: Either tCDD or tODD must be satisfied. 20: tT is measured between VIH(min) and VIL(max).
MIT-DS-0094-0.5
MITSUBISHI ELECTRIC
( 7 / 20 )
27/Feb./1997
Preliminary Spec.
Specifications subject to change without notice.
MITSUBISHI LSIs
MH8V724AWZJ -5, -6
FAST PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM
Limits
Read and Refresh Cycles
Symbol tRC tRAS tCAS tCSH tRSH tRCS tRCH tRRH tRAL tOCH tORH Parameter Read cycle time /RAS low pulse width /CAS low pulse width /CAS hold time after /RAS low /RAS hold time after /CAS low Read Setup time after /CAS high Read hold time after /CAS low Read hold time after /RAS low Column address to /RAS hold time /CAS hold time after /OE low /RAS hold time after /OE low Min 90 50 15 50 15 0 0 10 25 13 13 -5 Max 10000 10000 Min 110 60 15 60 15 0 0 10 30 15 15 -6 Max 10000 10000 ns ns ns ns ns ns ns ns ns ns ns Unit
(Note 21) (Note 21)
Note 21: Either tRCH or tRRH must be satisfied for a read cycle.
Write Cycle (Early Write and Delayed Write)
Limits Symbol tWC tRAS tCAS tCSH tRSH tWCS tWCH tCWL tRWL tWP tDS tDH tOEH Parameter Write cycle time /RAS low pulse width /CAS low pulse width /CAS hold time after /RAS low /RAS hold time after /CAS low Write setup time before /CAS low (Note 23) Write hold time after /CAS low /CAS hold time after /W low /RAS hold time after W low Write pulse width Data setup time before /CAS low or W low Data hold time after /CAS low or W low /OE hold time after /W low Min 90 50 15 50 15 0 10 15 15 10 0 10 13 -5 Max 10000 10000 Min 110 60 15 60 15 0 10 15 15 10 0 10 15 -6 Max 10000 10000 ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
MIT-DS-0094-0.5
MITSUBISHI ELECTRIC
( 8 / 20 )
27/Feb./1997
Preliminary Spec.
Specifications subject to change without notice.
MITSUBISHI LSIs
MH8V724AWZJ -5, -6
FAST PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM
Limits Parameter -5
(Note22)
Read-Write and Read-Modify-Write Cycles
Symbol tRWC tRAS tCAS tCSH tRSH tRCS tCWD tRWD tAWD tCWL tRWL tWP tDS tDH tOEH -6 Max 10000 10000 Min 150 95 50 95 50 0 30 75 45 15 15 10 0 10 15 Max 10000 10000 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Read write/read modify write cycle time /RAS low pulse width /CAS low pulse width /CAS hold time after /RAS low /RAS hold time after /CAS low Read setup time before /CAS low Delay time, /CAS low to /W low Delay time, /RAS low to /W low Delay time, address to /W low /CAS hole time after /W low /RAS hold time after /W low Write pulse width Data setup time before /W loe Data hold time after /W low /OE hold time after /W low
(Note23) (Note23) (Note23)
Min 130 85 50 85 50 0 30 65 40 15 15 10 0 10 10
Note 22: tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT. 23:tWCS, tCWD,tRWD ,tAWD and,tCPWD are specified as reference points only. If tWCStWCS(min) the cycle is an early write cycle and the DQ pins will remain high impedance throughout the entire cycle. If tCWDtCWD(min), tRWDtRWD (min), tAWDtAWD(min) and tCPWD tCPWD(min) (for Fast page mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address. If neither of the above condition (delayed write) is satisfied,the DQ (at access time and until /CAS or /OE goes back to VIH) is indeterminate.
Fast Page Mode Cycle (Read, Early Write, Read -Write, Read-Modify-Write Cycle) (Note 24)
Limits Symbol tPC tPRWC tRAS tCP tCPRH tCPWD Parameter Fast page mode read/write cycle time
Fast page mode read write/read modify write cycle time
-5 Min 35 70 85 5 30 30 Max Min 40 75 100 10 35 35
-6 Max
Unit ns ns ns ns ns ns
/RAS low pulse width for read write cycle /CAS high pulse width /RAS hold time after /CAS precharge Delay time, /CAS precharge to W low
(Note25) (Note26) (Note23)
51200 10
51200 15
Note 24: All previously specified timing requirements and switching characteristics are applicable to their respective Fast page mode cycle. 25: tRAS(min) is specified as two cycles of /CAS input are performed. 26: tCP(max) is specified as a reference point only. If tCP tCP(max),access time is controlled exclusively by tCAC.
/CAS before /RAS Refresh Cycle (Note 27)
Limits Symbol tCSR tCHR tRSR tRHR Parameter /CAS setup time before /RAS low /CAS hold time after /RAS low Read setup time before /RAS low Read hold time after /RAS low Min 5 10 10 10 -5 Max Min 10 10 10 10 -6 Max ns ns ns ns Unit
Note 27: Eight or more /CAS before /RAS cycles instead of eight /RAS cycles are necessary for proper operation of /CAS before /RAS refresh mode.
MIT-DS-0094-0.5
MITSUBISHI ELECTRIC
( 9 / 20 )
27/Feb./1997
Preliminary Spec.
Specifications subject to change without notice.
MITSUBISHI LSIs
MH8V724AWZJ -5, -6
FAST PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM
(Note 28)
Timing Diagrams Read Cycle
tRC tRAS VIH RAS VIL tCSH tCRP VIH CAS VIL tASR VIH Address VIL tRRH tRCS VIH W VIL tDZC VIH Hi-Z VIL tCAC tAA tCLZ
DQ (OUTPUTS)
tRP
tRCD
tRSH tCAS
tRPC
tCRP
tRAD tRAH tASC tCAH
COLUMN ADDRESS
tRAL tCPN
tASR
ROW ADDRESS
ROW ADDRESS
tRCH
tCDD
DQ (INPUTS)
tOFF
VOH Hi-Z VOL tRAC tDZO VIH tOEA tOCH tOEZ tODD
DATA VALID
Hi-Z
OE
VIL
tORH
Note 28
Indicates the don't care input. VIH(min)VINVIH(max) or VIL(min)VINVIL(max) Indicates the invalid output.
MIT-DS-0094-0.5
MITSUBISHI ELECTRIC
( 10 / 20 )
27/Feb./1997
Preliminary Spec.
Specifications subject to change without notice.
MITSUBISHI LSIs
MH8V724AWZJ -5, -6
FAST PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM
Write Cycle (Early write)
tWC tRAS VIH VIL tCSH tCRP VIH VIL tASR VIH VIL tASR tRAH tASC tCAH
COLUMN ADDRESS ROW ADDRESS
tRP
RAS
tRCD
tRSH tCAS
tRPC tCRP
CAS
Address
ROW ADDRESS
tWCS W VIH VIL tDS
DQ (INPUTS)
tWCH
tDH
VIH VIL
DATA VALID
DQ (OUTPUTS)
VOH Hi-Z VOL
OE
VIH VIL
MIT-DS-0094-0.5
MITSUBISHI ELECTRIC
( 11 / 20 )
27/Feb./1997
Preliminary Spec.
Specifications subject to change without notice.
MITSUBISHI LSIs
MH8V724AWZJ -5, -6
FAST PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM
Write Cycle (Delayed write)
tWC tRAS VIH RAS VIL tCSH tCRP VIH CAS VIL tASR tRAH tASC tCAH tASR
COLUMN ADDRESS ROW ADDRESS
tRP
tRCD
tRSH tCAS
tRPC tCRP
Address
VIH VIL
ROW ADDRESS
tCWL tRCS VIH W VIL tWCH tDZC
DQ (INPUTS)
tRWL tWP
tDS Hi-Z tCLZ
tDH
DATA VALID
VIH VIL
DQ (OUTPUTS)
VOH Hi-Z VOL tDZO tOEZ tODD tOEH Hi-Z
OE
VIH VIL
MIT-DS-0094-0.5
MITSUBISHI ELECTRIC
( 12 / 20 )
27/Feb./1997
Preliminary Spec.
Specifications subject to change without notice.
MITSUBISHI LSIs
MH8V724AWZJ -5, -6
FAST PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM
Read-Write, Read-Modify-Write Cycle
tRWC tRAS VIH RAS VIL tCSH tCRP VIH CAS VIL tASR tRAH tRAD tASC tCAH tASR tRCD tRSH tCAS tRPC tCRP tRP
Address
VIH VIL
ROW ADDRESS
COLUMN ADDRESS
ROW ADDRESS
tRCS VIH VIL
tAWD tCWD tRWD
tCWL tRWL tWP
W
tDS tDZC
DQ (INPUTS)
tDH
VIH VIL tCAC tAA tCLZ
Hi-Z
DATA VALID
DQ (OUTPUTS)
VOH Hi-Z VOL tRAC tDZO VIH VIL tOEA
DATA VALID
Hi-Z tODD tOEZ tOEH
OE
MIT-DS-0094-0.5
MITSUBISHI ELECTRIC
( 13 / 20 )
27/Feb./1997
Preliminary Spec.
Specifications subject to change without notice.
MITSUBISHI LSIs
MH8V724AWZJ -5, -6
FAST PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM
CAS before RAS Refresh Cycle
tRC tRP VIH RAS VIL tCSR tRAS tRAS
tRC tRP
tRPC VIH CAS VIL
tCHR
tRPC
tCSR
tCHR
tRPC
tCRP
tCPN tASR Address VIH VIL tRCH tRSR VIH W VIL tRHR tRSR tRHR tRCS
ROW ADDRESS COLUMN ADDRESS
DQ (INPUTS)
VIH VIL tOFF
DQ (OUTPUTS)
VOH VOL tOEZ VIH
Hi-Z
OE
VIL
MIT-DS-0094-0.5
MITSUBISHI ELECTRIC
( 14 / 20 )
27/Feb./1997
Preliminary Spec.
Specifications subject to change without notice.
MITSUBISHI LSIs
MH8V724AWZJ -5, -6
FAST PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM
Hidden Refresh Cycle (Read)
(Note 29)
tRC tRAS VIH RAS VIL tCRP VIH CAS VIL tRAD tASR VIH Address VIL tRCS tRAL VIH W VIL tDZC tRRH tRAH
ROW ADDRESS
tRC tRP tRAS tRP
tRCD
tRSH
tCHR
tASC
tCAH
COLUMN ADDRESS
tASR
ROW ADDRESS
tCDD
DQ (INPUTS)
VIH Hi-Z VIL tCAC tAA tCLZ Hi-Z VOL tRAC tDZO VIL tOEA tORH tOEZ tODD
DATA VALID
tOFF
DQ (OUTPUTS)
VOH Hi-Z
OE
VIH
Note 29: Early write, delayed write, read write or read modify write cycle is applicable instead of read cycle. Timing requirements and output state are the same as that of each cycle shown above.
MIT-DS-0094-0.5
MITSUBISHI ELECTRIC
( 15 / 20 )
27/Feb./1997
Preliminary Spec.
Specifications subject to change without notice.
MITSUBISHI LSIs
MH8V724AWZJ -5, -6
FAST PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM
Fast Page Mode Read Cycle
tRAS VIH RAS VIL tCSH tCRP VIH CAS VIL tRAD tASR VIH VIL tRAL tRCS VIH W VIL tDZC tDZC tDZC tRCH tRCS tRCH tRCS tRAH tASC tCAH
COLUMN-1
tRP
tPC tCAS tCP tCAS tCP
tRCD
tRSH tCAS
tCPRH tASC tCAH tASC tCAH tASR
ROW ADDRESS
Address
ROW ADDRESS
COLUMN-2
COLUMN-3
tRRH
tRCH
tCDD
DQ (INPUTS)
VIH Hi-Z VIL tCAC tAA tCLZ tOFF tAA tCLZ
DATA VALID-1 DATA VALID-2
Hi-Z tCAC tOFF tCAC tAA tCLZ
DATA VALID-3
tOFF
DQ (OUTPUTS)
VOH Hi-Z VOL tRAC tDZO VIL
tCPA tOEA tOCH tOEZ tOEA tOCH
tCPA tOEZ tOEA tOCH tOEZ
OE
VIH tDZO tODD tODD tDZO tORH tODD
MIT-DS-0094-0.5
MITSUBISHI ELECTRIC
( 16 / 20 )
27/Feb./1997
Preliminary Spec.
Specifications subject to change without notice.
MITSUBISHI LSIs
MH8V724AWZJ -5, -6
FAST PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM
Fast Page Mode Write Cycle (Early Write)
tRAS VIH RAS VIL tCSH tCRP VIH CAS VIL tASR tRAH tASC tCAH tASC tCAH tASC tCAH tRCD tCAS tCP tPC tCAS tCP tRSH tCAS
tRP
tASR
ROW ADDRESS
Address
VIH VIL
ROW ADDRESS
COLUMN-1
COLUMN-2
COLUMN-3
tWCS VIH W VIL tDS
DQ (INPUTS)
tWCH
tWCS
tWCH
tWCS
tWCH
tDH
DATA VALID-1
tDS
tDH
tDS
tDH
DATA VALID-3
VIH VIL
DATA VALID-2
DQ (OUTPUTS)
VOH Hi-Z VOL
OE
VIH VIL
MIT-DS-0094-0.5
MITSUBISHI ELECTRIC
( 17 / 20 )
27/Feb./1997
Preliminary Spec.
Specifications subject to change without notice.
MITSUBISHI LSIs
MH8V724AWZJ -5, -6
FAST PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM
Fast-Page Mode Write Cycle (Delayed Write)
tRAS VIH RAS VIL tCSH tCRP VIH CAS VIL tASR tRAH tASC tCAH tASC tCAH tRWL tCWL tRCD tCAS tCP tRSH tPC tCAS
tRP
tASR
ROW ADDRESS
Address
VIH VIL
ROW ADDRESS
COLUMN-1
COLUMN-2
tRCS VIH W VIL tWCH tDZC VIH Hi-Z VIL tDS
tCWL tWP
tPCS tWP
tWCH tDH
DATA VALID-1
tDZC tDS Hi-Z
tDH
DATA VALID-2
DQ (INPUTS)
tCLZ
DQ (OUTPUTS)
tCLZ Hi-Z tOEZ tODD tDZO tOEZ tODD tOEH Hi-Z
VOH Hi-Z VOL tDZO VIH
OE VIL
MIT-DS-0094-0.5
MITSUBISHI ELECTRIC
( 18 / 20 )
27/Feb./1997
Preliminary Spec.
Specifications subject to change without notice.
MITSUBISHI LSIs
MH8V724AWZJ -5, -6
FAST PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM
Fast Page Mode Read-Write,Read-Modify-Write Cycle
tRAS VIH VIL tCSH tCRP VIH VIL tASR tRAD tRAH tASC tCAH tASC tCAH tCWL tRCD tCAS tCP CAS tPRWC tCAS
tRP
RAS
tRWL
tASR
ROW ADDRESS
VIH Address VIL
ROW ADDRESS
COLUMN-1
COLUMN-2
tAWD tRCS VIH VIL tRWD tDZC
DQ (INPUTS)
tAWD tCWL tWP tRCS tCWD tWP
tCWD
W
tCPWD tDS tDH
DATA VALID-1
tDZC tDS Hi-Z tCAC tAA tCLZ
tDH
DATA VALID-2
VIH VIL Hi-Z tCAC tAA tCLZ
DQ (OUTPUTS)
VOH Hi-Z VOL tRAC tDZO VIH VIL tOEA
DATA VALID-1
Hi-Z tODD tOEZ tDZO tOEA tCPA
DATA VALID-1
Hi-Z tODD tOEZ tOEH
OE
MIT-DS-0094-0.5
MITSUBISHI ELECTRIC
( 19 / 20 )
27/Feb./1997
Preliminary Spec.
Specifications subject to change without notice.
MITSUBISHI LSIs
MH8V724AWZJ -5, -6
FAST PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM
Unit:mm 133.35
Package outline
8.6MAX
2-R2.0
3.0
127.35
25.4
4.0
17.78 3.0
2.0
2-o3.0
2.0 6.35 29x1.27=36.83 6.35 43x1.27=54.61
1.27 1.27
8.89 24.495
9x1.27=11.43 42.18
MIT-DS-0094-0.5
MITSUBISHI ELECTRIC
( 20 / 20 )
4.0 3.0 17.78
27/Feb./1997

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